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Altera_Forum's avatar
Altera_Forum
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13 years ago

Reading a file and storing the data into a record (VHDL)

Super Newb here....

So I am having issues of how to write a function that will input a line and break it into a record. I feel like it is something simple like how to store a line into an array but I dont fully understand

So here is the code I wrote so far 


Library ieee;
Use std.textio.all;
Use ieee.numeric_std.all;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity Project_Work is end;
Architecture code of Project_Work is 
    
    Variable L_In: Line;
    File Blank_File: text is in "Blank.txt";
    
            
    Begin 
        While not endfile (Blank_File) loop
            readline(Blank_File,L_in);
        End Loop;
        
    Function PARSE_VEC (L_In: Line)
                        Return record is
        Type in_vec is record
        In_1:             std_logic_vector(3 downto 0);
        In_2:             std_logic_vector(3 downto 0);
        Parity:            std_logic;
        Expected_Out:    std_logic_vector(7 downto 0);
        End Record in_vec;
    
    End PARSE_VEC;

So the text it see are like

"0000 0000 0 00000000

1111 1101 1 11011011

0010 1100 1 00101001"

Ant suggestions or ideas are great :)

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    There are many webpages showing how to do file access from VHDL, and I'm certainly not an expert, but I think that after you have read a line in (say, "0010 1100 1 00101001"), you then need to perform separate reads for each element. 

    
--After the process statement
variable v_in1 : std_logic_vector(3 downto 0);
variable v_in2 : std_logic_vector(3 downto 0);
variable v_parity : std_logic;
variable v_expected_output : std_logic_vector(7 downto 0);
.
.
.
readline(Blank_File,L_in); -- Reads the whole line in "0010 1100 1 00101001"
read(L_in, v_in1); -- Puts "0010" into v_in1
read(L_in, v_in2); -- Puts "1100" into v_in2
read(L_in, v_parity); -- Puts "1" into v_parity
read(L_in, v_expected_output); -- Puts "00101001" into v_expected_ouput

    This code reads the different sections into separate variables. It might be possible to read them directly into a record but I've never tried it.

    Apart from that your code is not properly structured. Perhaps you might want to get a book on VHDL or browse the web for examples?
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Are you sure you've copied this code correctly, there are many errors:

    1. You cannot have variables in an architecture

    2. You cannot have a while loop outside a process/function/procedure

    3. function PARSE_VEC cannot return a "record", it has to return a specfied type.

    But yes, you can easily do what you want, basically exactly like chnaideur said. If you can repost your fixed code, and have a good stab, we can help more when you get stuck.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    Are you sure you've copied this code correctly, there are many errors:

    1. You cannot have variables in an architecture

    2. You cannot have a while loop outside a process/function/procedure

    3. function PARSE_VEC cannot return a "record", it has to return a specfied type.

    But yes, you can easily do what you want, basically exactly like chnaideur said. If you can repost your fixed code, and have a good stab, we can help more when you get stuck.

    --- Quote End ---

    Ok here is my incomplete version so far 

    
Library ieee;
Use std.textio.all;
Use ieee.numeric_std.all;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity Homework05 is end;
Architecture code of Homework05 is 
	
	Signal L_In: Line;
	File Blank_File: text is in "Blank.txt";
	
	
Begin
	Read:Process
		While not endfile (Blank_File) loop
			readline(Blank_File,L_in);
		End Loop;
	End Process;
	
	Type in_vec is record
		In_1: 			std_logic_vector(3 downto 0);
		In_2: 			std_logic_vector(3 downto 0);
		Parity:			std_logic;
		Expected_Out:	std_logic_vector(7 downto 0);
	End Record in_vec;
	
Function PARSE_VEC (L_In: Line)
Return in_vec is
	Begin
		Variable In_1Hold:	 	string (3 downto 0);
		Variable In_2Hold:	 	string (3 downto 0);
		Variable Hold2: 		string (7 downto 0);
		Variable Char:			character;
				
		Read(L_in,In_1Hold);
		In_1 <= to_std_logic_vector(In1_Hold);
	
		Read(L_in,In_2Hold);
		In_2 <= to_std_logic_vector(In2_Hold);
		
		Read(L_in, char);
		Parity <= to_std_logc_vector(Char);
		
		Read(L_in, Hold2);
		Expected_Out <=to_std_logic_vector(Hold2);
	
	End PARSE_VEC; 
End Code;

    Do I need to worry about blank spaces in between each part of the code?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Yeah, I have a book but it does not give examples for functions and records

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I'm sorry to say this but there are many problems with the code... Looks like you need a different approach as you don't seem to understand the fundamental concepts of digital electronics, especially of combinational and sequential logic. How about starting from the beginning of the book, the really 'simple' stuff? Or an on-line tutorial such as this one:

    http://www.doulos.com/knowhow/vhdl_designers_guide/an_example_design_entity/

    followed by

    http://www.doulos.com/knowhow/vhdl_designers_guide/tips/sequential_processes/

    Once you understand the core basics, perhaps it might be worth looking at a more complex example such as this led blinker:

    http://www.armadeus.com/wiki/index.php?title=simple_blinking_led

    With knowledge from the first link, you could design a test bench for it, see how it works. I'm just saying this because writing a test-bench to read a file with no background knowledge will take a very long time and will be frustrating!

    But here just a few tips:

    - in your case, functions and signals should be defined in the architecture header.

    - variables should be defined in the process header for processes and in the function header for functions.