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Are you sure you've copied this code correctly, there are many errors:
1. You cannot have variables in an architecture
2. You cannot have a while loop outside a process/function/procedure
3. function PARSE_VEC cannot return a "record", it has to return a specfied type.
But yes, you can easily do what you want, basically exactly like chnaideur said. If you can repost your fixed code, and have a good stab, we can help more when you get stuck.
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Ok here is my incomplete version so far
Library ieee;
Use std.textio.all;
Use ieee.numeric_std.all;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity Homework05 is end;
Architecture code of Homework05 is
Signal L_In: Line;
File Blank_File: text is in "Blank.txt";
Begin
Read:Process
While not endfile (Blank_File) loop
readline(Blank_File,L_in);
End Loop;
End Process;
Type in_vec is record
In_1: std_logic_vector(3 downto 0);
In_2: std_logic_vector(3 downto 0);
Parity: std_logic;
Expected_Out: std_logic_vector(7 downto 0);
End Record in_vec;
Function PARSE_VEC (L_In: Line)
Return in_vec is
Begin
Variable In_1Hold: string (3 downto 0);
Variable In_2Hold: string (3 downto 0);
Variable Hold2: string (7 downto 0);
Variable Char: character;
Read(L_in,In_1Hold);
In_1 <= to_std_logic_vector(In1_Hold);
Read(L_in,In_2Hold);
In_2 <= to_std_logic_vector(In2_Hold);
Read(L_in, char);
Parity <= to_std_logc_vector(Char);
Read(L_in, Hold2);
Expected_Out <=to_std_logic_vector(Hold2);
End PARSE_VEC;
End Code;
Do I need to worry about blank spaces in between each part of the code?
Honored Contributor
