Reading a file and storing the data into a record (VHDL)

There are many webpages showing how to do file access from VHDL, and I'm certainly not an expert, but I think that after you have read a line in (say, "0010 1100 1 00101001"), you then need to perform separate reads for each element.

--After the process statement
variable v_in1 : std_logic_vector(3 downto 0);
variable v_in2 : std_logic_vector(3 downto 0);
variable v_parity : std_logic;
variable v_expected_output : std_logic_vector(7 downto 0);
.
.
.
readline(Blank_File,L_in); -- Reads the whole line in "0010 1100 1 00101001"
read(L_in, v_in1); -- Puts "0010" into v_in1
read(L_in, v_in2); -- Puts "1100" into v_in2
read(L_in, v_parity); -- Puts "1" into v_parity
read(L_in, v_expected_output); -- Puts "00101001" into v_expected_ouput

This code reads the different sections into separate variables. It might be possible to read them directly into a record but I've never tried it.

Apart from that your code is not properly structured. Perhaps you might want to get a book on VHDL or browse the web for examples?