Read binary file to binary vector array

Reading binary files is typical for simulation (Modelsim), eg., see lfsr_tb.vhd in this tutorial:

http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf

http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial_src.zip

Here's the relevant code snippets:

	-- File parameters
    	subtype byte_t is character;
    	type binary_file_t is file of byte_t;
    	file binary_file : binary_file_t;
    	variable status : file_open_status;
    	variable byte : byte_t;
        ...
	-- Open the file
	file_open(status, binary_file, PRBS_FILE_NAME, READ_MODE);
	assert status = OPEN_OK
		report "File open for read failed!"
		severity failure;
	-- Read the data
	index := 0;
    	while not  endfile(binary_file) loop
		-- Read a byte
		read(binary_file, byte);
		-- Serialize
		if (index + 8 < PRBS_LENGTH) then
			prbs_sequence(index+7 downto index)
				:= to_slv(character'pos(byte), 8);
			index := index + 8;
		else
			-- Convert the last bits
			prbs_sequence(PRBS_LENGTH-1 downto index)
				:= to_slv(character'pos(byte),
					PRBS_LENGTH-index);
			exit;
		end if;
	end loop;
	file_close(binary_file);

For synthesis, the use of file I/O will be more restrictive, eg., you might be able to use it to initialize a signal.

What are you trying to do? If you need the binary data at run time, would a RAM (or ROM) component be more appropriate?

Cheers,

Dave

Ah yes I failed to mention that I will be writing this binary data to the SDRAM on my DE2-115, and will therefore need to synthesize it.

So how should I use file I/O to initialize a signal with the binary data?

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Ah yes I failed to mention that I will be writing this binary data to the SDRAM on my DE2-115, and will therefore need to synthesize it.

So how should I use file I/O to initialize a signal with the binary data?

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You cannot initialize external memory from the .sof image. You could however store the SDRAM contents in the external configuration device (EPCS, flash, whatever) and have your logic copy data from the configuration device to SDRAM after configuration. Personally, I would just use your development machine to write the contents to SDRAM, see this tutorial:

http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial

Cheers,

Dave

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You cannot initialize external memory from the .sof image.

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Hmm I don't think I'm quite trying to do that?

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You could however store the SDRAM contents in the external configuration device (EPCS, flash, whatever) and have your logic copy data from the configuration device to SDRAM after configuration.

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I don't have any contents in SDRAM right now. My data is an external binary txt file and I need to figure out how to read that into a binary vector array (thereby initializing it) and then use that inside a process where I write the data to SDRAM. Is that what you're referring to which can't be done?

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Hmm I don't think I'm quite trying to do that?

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You just don't think that is what you are asking :)

The Quartus synthesis tool generates an .sof image for the FPGA. You were asking how to get Quartus to use a file - the only reason to do that would be to have that file used for synthesis.

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I don't have any contents in SDRAM right now. My data is an external binary txt file and I need to figure out how to read that into a binary vector array (thereby initializing it) and then use that inside a process where I write the data to SDRAM. Is that what you're referring to which can't be done?

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What "can be done" depends on your hardware.

Assuming your FPGA is sitting on a board with only a JTAG connection connecting it to your host PC, how many ways can you think of to get data from a text file on your hard-drive onto the FPGA?

If however your FPGA is on a PCIe board sitting inside a PC, and you know how to write device drivers, then you could transfer data over PCI to the SDRAM (via the FPGA), and have your FPGA logic access the SDRAM after the data is written.

If you describe your hardware, I'll try to help you figure out what you can do. You should first read the tutorial I provide the link for, things may become a little clearer to you then.

Cheers,

Dave

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For synthesis, the use of file I/O will be more restrictive, eg., you might be able to use it to initialize a signal.

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Unfortunately Quartus does not support this - I raised a support request a long time ago for this to be sorted, as you can use the readmemh to initialise a ram from a text file in verilog, and Xilinx support the use of textio for initialisation of internal rams, but Quartus just wont.