Forum Discussion
Altera_Forum
Honored Contributor
12 years ago --- Quote Start --- For synthesis, the use of file I/O will be more restrictive, eg., you might be able to use it to initialize a signal. --- Quote End --- Unfortunately Quartus does not support this - I raised a support request a long time ago for this to be sorted, as you can use the readmemh to initialise a ram from a text file in verilog, and Xilinx support the use of textio for initialisation of internal rams, but Quartus just wont.