Strange issues on FPGA

I have another question. Originally, I had a Tx/Rx transmission module receiver, but I encountered a deadlock issue during testing, so I switched to parallel transmission. This time, I deeply realized that when receiving external signals, it’s important to process and wait for stability first.

I modified the module receiver using the same concept, and although it doesn't lead to illegal states causing deadlock, it sometimes fails to correctly receive data from Rx.

I am currently testing and inferring that the issue is also caused by the input changing simultaneously with the clock edge.

My Tx/Rx architecture:

My Tx transmission format is:

Start bit + 12bit data(LSB to MSB) + Stop bit = total 14bit, refer to:

My Receiver Code:

module receiver.v

Result

On the left is the SPI data, which is sent through Tx after reversing the MSB, and on the right is the data received by Rx:

I have confirmed that the timing and state are both normal:

First data:

Sixth data:

Observing the execution time of the shift_reg based on the changes in GPIO.

			if(current_state == RECEIVE) begin
				shift_reg <= {RX_sync, shift_reg[11:1]};
				bit_count <= bit_count + 1;
				gpio <= ~gpio;
			end

Due to the use of a synchronization register, the GPIO will be delayed by one clock cycle.

	//* ----- Synchronization Register ----- *//
	reg [1:0] rx_sync;

	// Registers are updated on every rising clock edge
	always @(posedge clk) begin
		 // Synchronize the external signal step by step to the FPGA internal clock
		 rx_sync <= {rx_sync[0], rx};
	end

	// Sync Signal
	wire RX_sync = rx_sync[1];

I initially had no way to solve this issue, but referring to a recent discussion[1], if I use oversampling during Rx reception, it should help avoid the problem of the input Rx changing simultaneously with the clock edge.

So generally, when designing a receiver, oversampling is used to solve this issue?

[1] SYNCHRONIZED RS232 DATA CORRUPTED