Forum Discussion

Ranjith21's avatar
Ranjith21
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Quartus 23.4 shows 0.0 BER but negative eye height values

Hi, I am running BER test for 2 FPGAs. I am transmitting from Tx pin of first FPGA and receiving on Rx pin on second FPGA. Using Quartus 23.4 here. Both are Agilex F-tile F-series FPGAs. There is ...
Platform
ZiYing_Intel's avatar
ZiYing_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi Ranjith,


Please do let me know if there is any update on the BER value when you adjust the main tap value.


Best regards,

zying


Ranjith21's avatar
Ranjith21
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hi @ZiYing_Intel

I am sweeping different values for main tap as shown in the attached PDF. Still negative eye height with zero BER exists, please refer .pdf attached

Thanks,

Ranjith

  • Ranjith21's avatar
    Ranjith21
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    @ZiYing_Intel

    Here is another autosweep showing the same issue

    Attached

    Thanks,

    Ranjith