Forum Discussion
BobA
New Contributor
New ContributorHow to fix "Warning (10030): Net "microcode1.data_a" at MAX10CPU.sv(10) has no driver or initial val
Hi, I'm using Quartus Prime Lite 24.1 and Synplify Pro, targeting the MAX 10 10M08SCE144A7G. My SystemVerilog code is: module MAX10CPU(
input [15:0] address,
output [7:0] mc,
input noe
);
...
You can use synthesis attributes: https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vlog/vlog_file_dir_ram_init.htm
sstrell
Super Contributor
Super ContributorI've always used .dat for this. I've never actually heard of .mem. This article uses .txt actually: https://fpgacoding.com/test-bench-data-files-in-verilog/
BobANew Contributor
New ContributorIt's just the extension. I know the file's contents are in $readmemh's format.
The bigger concern is that the 'initial' block doesn't get synthesized. But is there another way to initialize memory in the synthesized Verilog?
