New Contributor
Super ContributorHi @Ranesh ,
In your updated code, there are differences between the lines 144 and 151.
Line 144:
s_output_data[c] <= s_in_data[((W_MODULE_DATA - ((c - c_IN_DESC_BYTE_CNT) * 8)) - 1) -: 8];
Line 151:
s_output_data[d] <= s_in_data[((W_MODULE_DATA - ((d - s_outbytecount) * 8))- 1) -: 8];
For line 151, if change s_outbytecount to c_IN_DESC_BYTE_CNT also produce the error below:
Error(13224): Verilog HDL or VHDL error at vector_capture.sv(151): index 136 is out of range [15:0] for 's_in_data'
For line 144, if change c_IN_DESC_BYTE_CNT to s_in_empty and with previous if (c < (c_IN_DESC_BYTE_CNT + (c_IN_DATA_BYTE_CNT - s_in_empty))), there'll be no error produced as well.
So you're comparing two different things. Let me know if you have any further concern.
Thanks,
Best Regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
New ContributorHi Sheng,
Please don't compare line 144 and 151, they are not causing this error. If you change line 144 to have
(c - c_IN_DESC_BYTE_CNT) > 2, it will produce negative index for s_in_data and similarly, in line 151, if
(d - s_outbytecount) > 2, it will produce negative index for s_in_data. This is because W_MODULE_DATA = 16.
Please don't change any of these lines.
Please compare lines 142 (commented), 143 with line 150.
If line 142 is used, the compiler produced following error:
Error(13224): Verilog HDL or VHDL error at vector_capture.sv(144): index -8 is out of range [15:0] for 's_in_data'
If line 143 used, which does not use s_in_empty in for loop if statement, the compiler does not produced any error
For this error, you have mentioned:
You can't use logic type s_in_empty in for loop if statement.
Please note that line 150 is using a logic type s_outbytecount in for loop if statement, which does not cause any synthesis error. This shows that a logic type can be used in for loop if statement.
Thank you.
Regards,
Ranesh
