Ranesh
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Re: Analysis & Synthesis Error(13224): Verilog HDL or VHDL error "..:" index -8 is out of range [15:0]..
Hi Sheng, Please note that the expression if (c < (c_IN_DESC_BYTE_CNT + (c_IN_DATA_BYTE_CNT - s_in_empty))) is bound by the expression for (int c = c_IN_DESC_BYTE_CNT; c < c_OUT_DATA_BYTE_CNT; c++). This limits c not to be below c_IN_DESC_BYTE_CNT, which is 26. So in the expression s_output_data[c] <= s_in_data[((W_MODULE_DATA - ((c - c_IN_DESC_BYTE_CNT) * 8)) - 1) -: 8], which is bound by the expression that you have mentioned, c can only be 26 or 27, because s_in_empty is single bit signal and c_IN_DATA_BYTE_CNT = 2. I am re-attaching my explanation in word document for you and the expert Regards, Ranesh6.8KViews0likes0CommentsRe: Analysis & Synthesis Error(13224): Verilog HDL or VHDL error "..:" index -8 is out of range [15:0]..
Hi Sheng, There was a mistake in last line of my last reply: The lie "Please concentrate only on line 142, 143 (these if statements are bound by for loop in line 140) and 151(this if statement is bound by for loop in line 150)." is not correct. It should be "Please concentrate only on line 142, 143 (these if statements are bound by for loop in line 140 and 145) and 150 (this if statement is bound by for loop in line 148 and 152)." Thank you. Regards, Ranesh7.3KViews0likes0CommentsRe: Analysis & Synthesis Error(13224): Verilog HDL or VHDL error "..:" index -8 is out of range [15:0]..
Hi Sheng, You cannot change s_outbytecount to 0 only in line 151, you have to change s_outbytecount in line 150 to 0 as well, because line 151 is constrained by line 150.. By changing value of s_outbytecount to 0 only in line 151, you are making logical error and regardless of compiler this would lead to an error. Please do not play with s_outbytecount in line 151. You can notice that s_outbytecount is calculated in line 146 and 153. If you want to change s_outbytecount to see line 151 behavior, you have to calculate (d - s_outbytecount) value in line 151. W_MODULE_DATA = 16, c_OUT_DATA_BYTE_CNT = 32, c_IN_DATA_BYTE_CNT = 2 and Line 148 to152: 148: for (int d = 0; d < c_OUT_DATA_BYTE_CNT; d++) 149: begin 150: if ((d >= s_outbytecount) && (d < (s_outbytecount + c_IN_DATA_BYTE_CNT))) 151: s_output_data[d] <= s_in_data[((W_MODULE_DATA - ((d - s_outbytecount) * 8))- 1) -: 8]; 152: end In line 148 d can take 0 to 31 In line 151 d is constrained to be from s_outbytecount to (s_outbytecount + c_IN_DATA_BYTE_CNT) - 1 Since W_MODULE_DATA = 16, ((d - s_outbytecount) * 8)) can take only 0 or 8. when ((d - s_outbytecount) * 8)) = 0, ((W_MODULE_DATA - ((d - s_outbytecount) * 8))- 1) = 15 when ((d - s_outbytecount) * 8)) = 8, ((W_MODULE_DATA - ((d - s_outbytecount) * 8))- 1) = 7 So line 151 would not have any errors In other words, ((d - s_outbytecount) * 8)) cannot be greater than 8 or less than 0. Please concentrate only on line 142, 143 (these if statements are bound by for loop in line 140) and 151(this if statement is bound by for loop in line 150). Regards, Ranesh7.3KViews0likes1CommentRe: Analysis & Synthesis Error(13224): Verilog HDL or VHDL error "..:" index -8 is out of range [15:0]..
Hi Sheng, Please don't compare line 144 and 151, they are not causing this error. If you change line 144 to have (c - c_IN_DESC_BYTE_CNT) > 2, it will produce negative index for s_in_data and similarly, in line 151, if (d - s_outbytecount) > 2, it will produce negative index for s_in_data. This is because W_MODULE_DATA = 16. Please don't change any of these lines. Please compare lines 142 (commented), 143 with line 150. If line 142 is used, the compiler produced following error: Error(13224): Verilog HDL or VHDL error at vector_capture.sv(144): index -8 is out of range [15:0] for 's_in_data' If line 143 used, which does not use s_in_empty in for loop if statement, the compiler does not produced any error For this error, you have mentioned: You can't use logic type s_in_empty in for loop if statement. Please note that line 150 is using a logic type s_outbytecount in for loop if statement, which does not cause any synthesis error. This shows that a logic type can be used in for loop if statement. Thank you. Regards, Ranesh7.4KViews0likes0CommentsRe: Analysis & Synthesis Error(13224): Verilog HDL or VHDL error "..:" index -8 is out of range [15:0]..
Hi Sheng, I have noticed that if I eliminate s_in_empty in the if condition, there is no synthesis error. In another segment of my vector_capture.sv I am using an internal counter that is to count number bytes in s_output_data and there is no synthesis error in this line. I have attached modified vector_capture.sv for your consideration. Please note that line 142 is commented and 143 is introduced to avoid previous synthesis error. Also, please note that line 147 to line 153 are introduced with s_outbytecount, but the line 150 if condition is not produce any synthesis error as before. Regards, Ranesh7.4KViews0likes1CommentRe: Analysis & Synthesis Error(13224): Verilog HDL or VHDL error "..:" index -8 is out of range [15:0]..
Hi Sheng, Thank you for your answer. What you are saying is correct, but it cannot be the cause of this error. ========== Lines 21, 26 and 27 of vector_capture_synth_top.sv are: 21: parameter W_MCDMA_DATA = 256; 26: parameter W_MODULE_DATA = 16; // Supported data widths (8 bits to 256 bits) power of 2 (2^3 to 2^8) 27: parameter W_MODULE_DESC = 204; // less than or equal to 256 ========== Lines 66 to 70 of vector_capture.sv are: 66: localparam c_DESCBYTEALIGNBITS = ((W_MODULE_DESC % 😎> 0) ? (8 - (W_MODULE_DESC % 8)) : 3'b0; c_DESCBYTEALIGNBITS = ((204 % 😎> 0) ? (8 - (204 % 8)) : 3'b0 c_DESCBYTEALIGNBITS = (4 > 0) ? (8 - 4) : 3'b0 c_DESCBYTEALIGNBITS = 4 67: logic [((W_MODULE_DESC + c_DESCBYTEALIGNBITS) - 1):0] s_in_desc; // Configuration bus from feeder module logic [((204 + 4) - 1):0] s_in_desc; logic [207:0] s_in_desc; 68: localparam c_IN_DESC_BYTE_CNT = ((W_MODULE_DESC + c_DESCBYTEALIGNBITS)/8); c_IN_DESC_BYTE_CNT = ((204 + 4)/8) c_IN_DESC_BYTE_CNT = ((208)/8) c_IN_DESC_BYTE_CNT = 26 69: localparam c_IN_DATA_BYTE_CNT = (W_MODULE_DATA/8); c_IN_DATA_BYTE_CNT = (16/8) c_IN_DATA_BYTE_CNT = 2 70: localparam c_OUT_DATA_BYTE_CNT = (W_MCDMA_DATA/8); c_OUT_DATA_BYTE_CNT = (256/8) c_OUT_DATA_BYTE_CNT = 32 ========== Lines 140 to 144 of vector_capture.sv are: 140: for (int c = c_IN_DESC_BYTE_CNT; c < c_OUT_DATA_BYTE_CNT; c++) (int c = 26; c < 32; c++) Within this for loop, c can take only 26, 27, 28, 29, 30 and 31 141: begin 142: if (c < (c_IN_DESC_BYTE_CNT + (c_IN_DATA_BYTE_CNT - s_in_empty))) (c < (26 + (2 - s_in_empty))) (c < (28 - s_in_empty)) Note: s_in_empty is a single bit. Within this if statement: If s_in_empty = 0, (c < (28 - 0)) and c can be either 26 or 27 If s_in_empty = 1, (c < (28 - 1)) and c can be either 26 143: s_output_data[c] <= s_in_data[((W_MODULE_DATA - ((c - c_IN_DESC_BYTE_CNT) * 8)) - 1) -: 8]; If c takes 26 s_output_data[26] <= s_in_data[((16 - ((26 - 26) * 8)) - 1) -: 8]; s_output_data[26] <= s_in_data[((16 - ((0) * 8)) - 1) -: 8]; s_output_data[26] <= s_in_data[((16 - (0) - 1) -: 8]; s_output_data[26] <= s_in_data[((16 - 1) -: 8]; s_output_data[26] <= s_in_data[15 -: 8]; s_output_data[26] <= s_in_data[15 : 8]; If c takes 27 s_output_data[26] <= s_in_data[((16 - ((27 - 26) * 8)) - 1) -: 8]; s_output_data[26] <= s_in_data[((16 - ((1) * 8)) - 1) -: 8]; s_output_data[26] <= s_in_data[((16 - (8) - 1) -: 8]; s_output_data[26] <= s_in_data[((8 - 1) -: 8]; s_output_data[26] <= s_in_data[7 -: 8]; s_output_data[26] <= s_in_data[7 : 0]; 144: end From the above calculations, c cannot take any values that drives index of s_in_data to be -8. Regards, Ranesh7.5KViews0likes0Comments