Analysis & Synthesis Error(13224): Verilog HDL or VHDL error "..:" index -8 is out of range [15:0]..

Hi Sheng,

I have noticed that if I eliminate s_in_empty in the if condition, there is no synthesis error. In another segment of my vector_capture.sv I am using an internal counter that is to count number bytes in s_output_data and there is no synthesis error in this line.

I have attached modified vector_capture.sv for your consideration.

Please note that line 142 is commented and 143 is introduced to avoid previous synthesis error.

Also, please note that line 147 to line 153 are introduced with s_outbytecount, but the line 150 if condition is not produce any synthesis error as before.

Regards,

Ranesh