Occasional Contributor
Super ContributorDo you have further queries?
Occasional Contributorin my project, all ram is inferred to M20K by quartus eda tool. the ram behavior as follow:
always @(posedge clk) begin
if (ram_wra) data[ram_addra] <= wrp_dina;
end
always @(posedge clk) begin
if (rdb_c) wrp_doutb <= data[addrb];
end
the ram hierarchy as follow: x_blk_wk|x_eth_wrap|x_tx_dp_synczr|cdc.x_afifo|use_ram.x_afifo_ram_sp_wrap|x_ram_2p_2clk|data_rtl_0|auto_generated|altera_syncram_impl1|ram_block2a2
The hierarchical name of the RAM changes after each compilation. It was data_rtl_0 in the previous build and becomes data_rtl_1 in the next one.
