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senwang
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1 year ago

R-tile intel FPGA IP for compute express link(CXL) testbench has an AVY_ERROR.

Hi, hope you have a nice day! I have a problem when using the R-tile intel FPGA IP for compute express link(CXL) testbench. The testbench is generated through Quartus Prime 24.3. The CXL ip version ...
Simulation
senwang's avatar
senwang
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1 year ago

Hi RongYuan，

Thank you for your suggestions!
Below is the confirmation and analysis based on your requests:

VCS Tools and related licenses (AVERY_PCIE/AVERY_PLI) have all been configured with absolute paths in environment variables（the user guide mentions）。

In the 24.3 version of Quartus that I am using, the PIPE mode is enabled by default and does not involve this issue.


I would like to know if it is possible to determine where the problem may have occurred through this AVY_ERROR analysis.

Thanks