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senwang's avatar
senwang
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1 year ago

R-tile intel FPGA IP for compute express link(CXL) testbench has an AVY_ERROR.

Hi, hope you have a nice day! I have a problem when using the R-tile intel FPGA IP for compute express link(CXL) testbench. The testbench is generated through Quartus Prime 24.3. The CXL ip version ...
Simulation
RongY_altera's avatar
RongY_altera
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1 year ago

Hi,

Please confirm that you have absolute paths for all licenses setup as shown in "4.1.1. VCS Tools and License".


Also confirm PIPE Mode Simulation is enabled before generating an example design.


Regards,

Rong