I wrote code in ModelSim and this code generate wave, who I expected, but Quartus genrate error Error (10822): HDL error at klaw.vhd(110): couldn't implement registers for assignments on this clock edge What should I think about this?

--- Quote Start --- What should I think about this? --- Quote End --- VHDL code isn't always synthesizable. If you try e.g. to assign a signal on both clock edges, it doesn't work in FPGA hardware. Rember that HDL means hardware description language. If no suitable hardware exist for your code, it can't be synthesized.

Ok, but I use 2 clocks with one clock edges. This isn't synthesizable?

--- Quote Start --- Ok, but I use 2 clocks with one clock edges. This isn't synthesizable? --- Quote End --- Do you mean, one signal is assigned depending on two different clock edges? Most likely not synthesizable. You should show a HDL code example for clarification.

Quartus throw error in done_ps2'event and done_ps2 = '1'. process(clk, rst) begin if( rst = '0') then Present_State <= Read_but; elsif( rising_edge(clk) ) then Present_State <= Next_State; end if; end process; process(Present_State, key1, key2, key3, done_ps2) begin case Present_State is when Read_but => code_choice <= "01"; if(key1 = '1') then code_temp <= PushF5; Next_State <= Push; elsif(key2 = '1') then code_temp <= PushLeft; Next_State <= Push; elsif(key3 = '1') then code_temp <= PushRight; Next_State <= Push; else Next_State <= Read_but; end if; when Push => start_ps2 <= '1'; if (done_ps2'event and done_ps2 = '1') then start_ps2 <= '0'; Next_State <= Break; code_choice <= "10"; end if; when Break => start_ps2 <= '1'; if (done_ps2'event and done_ps2 = '1') then start_ps2 <= '0'; Next_State <= Release; code_choice <= "01"; end if; when Release => start_ps2 <= '1'; if (done_ps2'event and done_ps2 = '1') then start_ps2 <= '0'; Next_State <= Read_but; end if; end case; end process;

Hi, Your second process is meant to be combinatorial and should not contain the done_ps2 edge(which is in wrong place anyway). done_ps2 is not a clock I assume. If you want to use clock edge it must be at beginning of process like your first process. rules of clock edge coding are strict for synthesis. If you want done_pse ris detection then you can do that by other ways.

Qurtus vs Modelsim | Altera Community

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Altera_Forum

Honored Contributor

16 years ago

I have problem. In wector file I have node Next_State, but in report whis value don't appear.

Compiler shown such a this mesagge

--- Quote Start ---

Warning: Compiler packed, optimized or synthesized away node "Next_State". Ignored vector source file node.

--- Quote End ---

What this mean?


process(clk, rst)
    begin
        if( rst = '0') then
            Present_State <= Read_but;
        elsif( rising_edge(clk) ) then
            Present_State <= Next_State;
        end if;
    end process;
    
    process(Present_State, key1, key2, key3, done)
    begin
        case Present_State is
        when Read_but =>
            start_ps2 <= '0';
            if(key1 = '1') then
    --            code_temp <= PushF5;
                code_choice <= "00";
                Next_State <= Push;
            elsif(key2 = '1') then
    --            code_temp <= PushLeft;
                code_choice <= "01";
                Next_State <= Push;
            elsif(key3 = '1') then
    --            code_temp <= PushRight;
                code_choice <= "11";
                Next_State <= Push;
            else
    --            code_temp <= (others => '0');
                code_choice <= "ZZ";
                Next_State <= Read_but;
            end if;
        when Push =>
            start_ps2 <= '1';
            if (done = '1') then
                start_ps2 <= '0';
                Next_State <= Break;
                code_choice <= "10";
            else
        --        code_temp <= (others => '0');
                code_choice <= "ZZ";
                Next_State <= Push;
            end if;
        when Break =>
            start_ps2 <= '1';
            if (done = '1') then
                start_ps2 <= '0';
                Next_State <= Release;
                code_choice <= "00";
            else
    --            code_temp <= (others => '0');
                code_choice <= "ZZ";
                Next_State <= Break;
            end if;
        when Release =>
            start_ps2 <= '1';
            code_choice <= "ZZ";
    --        code_temp <= (others => '0');
            if (done = '1') then
                start_ps2 <= '0';
                Next_State <= Read_but;
            else
                Next_State <= Release;
            end if;
        end case;
    end process;
    code <= PushF5 when code_choice = "00" else
            PushLeft when code_choice = "01" else
            PushRight when code_choice = "11" else
            ReleaseKey when code_choice = "10" else (others => 'Z');

And what mean this message?

--- Quote Start ---

Warning: Converted tri-state buffer "code[0]" feeding internal logic into a wire

--- Quote End ---

Altera_Forum
Honored Contributor
16 years ago
Next_State isn't a real signal in your design. It doesn't represent an FPGA resource. Present_State is the only real FSM signal, represented by a number of registers. They are loaded with a the new state vector on every clock edge depending on actual state and input conditions. Ony real signals can be shown in Quartus simulation are accessed by SignalTap II.

Also internal tri-state signals don't really exist in an FPGA. They can be used to describe internal connections, but are converted by the design compiler to multiplexers and other logic elements. The warning informs you about this fact.

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