Qurtus vs Modelsim

Next_State isn't a real signal in your design. It doesn't represent an FPGA resource. Present_State is the only real FSM signal, represented by a number of registers. They are loaded with a the new state vector on every clock edge depending on actual state and input conditions. Ony real signals can be shown in Quartus simulation are accessed by SignalTap II.

Also internal tri-state signals don't really exist in an FPGA. They can be used to describe internal connections, but are converted by the design compiler to multiplexers and other logic elements. The warning informs you about this fact.