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Altera_Forum's avatar
Altera_Forum
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15 years ago

Questions about Clock Control Block, Clock Divider and TimeQuest

Hi,

My design is like this: a 50MHZ clock inputs to one the PLLs in Cyclone III, the PLL will generate a 240MHZ that will pass through a CCB( Clock Control Block) for global clock network. Then the 240MHZ will be divided by 4 (via synchronous counter) to generate a 60MHZ FPGA_CLOCK, divided by 6(again via synchronous counter) to generate 40MHZ (the clock is actually programmable for 20MHZ, 30MHZ, 40MHZ and 60MHZ) ADC_CLOCK; The FPGA_CLOCK and ADC_CLOCK will pass a multiplexer(2:1) and a CCB to clock dual-port RAM. The FPGA_CLOCK will pass through a CCB to clcok internal registers. The ADC_CLOCK will pass through a CCB the a ouput pin to clock external ADC.

Here is my questions:

1) Are these Clock Control Blocks absolutely needed?

2) With TimeQuest, only the 50MHZ can be constrained by create_clock, and all other clocks should be constrained by create_generated_clock. Is this correct?

3) When a clock passes through a CCB, should I constrain its input and output clocks seperately? For example, in my design, the PLL output (240MHZ) passes through a CCB to clock dividers. I have "derive_pll_clocks" to constrain PLL's output that is the CCB's input. in sdc file already. Should I include the following sentence to constrain the CCB's output?

create_generated_clock -name CLK_240MHZ -source [get_nets {mCLOCK|mPLL|altpll_component|auto_generated|wire_pll1_clk[0]}] [get_nets {mCLOCK|mPLL_BUF|clk_ctl_altclkctrl_9nd_component|wire_clkctrl1_outclk}]

Thanks.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Why don't you use a single PLL ?

    Timequest will be able to better identify the clocks, and your circuit will have improved timing.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Dear CurrentSensor,

    first, I suggest you follow Amilcar's suggestion: use the PLL to generate the multiple clocks (each Cyclone III PLL can generate 5 clocks) instead of the dividers, as much as possible.

    Second, there's a CCB for each clock distribution network. Even if you don't use the ALT_CLKCTRL block, the CCB clocks will go through the CCBs.

    Third,

    you should use the CCB to perform clock multiplexing.

    Fourth

    yes, you need to use create_generated_clock for the generated clocks.

    Fifth,

    I'm not sure TimeQuest will automatically handle the clock multiplexing done by the CCB. If it doesn't, check the 2nd clock multiplexing example:

    http://www.altera.com/support/examples/timequest/exm-tq-clock-mux.html
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    Dear CurrentSensor,

    first, I suggest you follow Amilcar's suggestion: use the PLL to generate the multiple clocks (each Cyclone III PLL can generate 5 clocks) instead of the dividers, as much as possible.

    Cyclone III PLL can generate 5 clocks, but can you use all 5 at the same time? I looked at Figure 5-1. Clock Control Block at page 5-5 of the Handbook, only 2 of 5 can be routed to CCB, and then only one may be selected to go through Global network, am I missing anything here? May the 5 outputs of one PLL be routed to 5 different CCBs at the same time?

    Second, there's a CCB for each clock distribution network. Even if you don't use the ALT_CLKCTRL block, the CCB clocks will go through the CCBs.

    Do you mean a CCB will automatically be used by Quartus II for a clock signal? So ALT_CLKCTRL is not necessary at all?

    Third,

    you should use the CCB to perform clock multiplexing.

    By looking at Figure 5-1, if clock inputs are from FPGA clock pins or PLL outputs, then we can use CCB as a multiplexer. otherwise it's impossible, right?

    Fourth

    yes, you need to use create_generated_clock for the generated clocks.

    Assume a clock is generated by internal logic, and in order to use global clock network, it has to pass through a CCB, right? (Do we need to use ALT_CLKCTRL in this case?) After the clock pass through a CCB, should it be treated as a generated clock and constrained? In other words, does the TimeQuest think a CCB changes clock timing?

    Fifth,

    I'm not sure TimeQuest will automatically handle the clock multiplexing done by the CCB. If it doesn't, check the 2nd clock multiplexing example:

    By looking at the RTL schematic, the multiplexer is not implemented with a CCB.

    --- Quote End ---

    I'm a newbie in Altera FPGA. Sorry for these dumm questions and thank you for your helping.