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Altera_Forum's avatar
Altera_Forum
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15 years ago

Questions about Clock Control Block, Clock Divider and TimeQuest

Hi, My design is like this: a 50MHZ clock inputs to one the PLLs in Cyclone III, the PLL will generate a 240MHZ that will pass through a CCB( Clock Control Block) for global clock network. Then...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Why don't you use a single PLL ?

Timequest will be able to better identify the clocks, and your circuit will have improved timing.