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Altera_Forum
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15 years ago

Questions about Clock Control Block, Clock Divider and TimeQuest

Hi, My design is like this: a 50MHZ clock inputs to one the PLLs in Cyclone III, the PLL will generate a 240MHZ that will pass through a CCB( Clock Control Block) for global clock network. Then...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Dear CurrentSensor,

first, I suggest you follow Amilcar's suggestion: use the PLL to generate the multiple clocks (each Cyclone III PLL can generate 5 clocks) instead of the dividers, as much as possible.

Second, there's a CCB for each clock distribution network. Even if you don't use the ALT_CLKCTRL block, the CCB clocks will go through the CCBs.

Third,

you should use the CCB to perform clock multiplexing.

Fourth

yes, you need to use create_generated_clock for the generated clocks.

Fifth,

I'm not sure TimeQuest will automatically handle the clock multiplexing done by the CCB. If it doesn't, check the 2nd clock multiplexing example:

http://www.altera.com/support/examples/timequest/exm-tq-clock-mux.html