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Dear CurrentSensor,
first, I suggest you follow Amilcar's suggestion: use the PLL to generate the multiple clocks (each Cyclone III PLL can generate 5 clocks) instead of the dividers, as much as possible.
Cyclone III PLL can generate 5 clocks, but can you use all 5 at the same time? I looked at Figure 5-1. Clock Control Block at page 5-5 of the Handbook, only 2 of 5 can be routed to CCB, and then only one may be selected to go through Global network, am I missing anything here? May the 5 outputs of one PLL be routed to 5 different CCBs at the same time?
Second, there's a CCB for each clock distribution network. Even if you don't use the ALT_CLKCTRL block, the CCB clocks will go through the CCBs.
Do you mean a CCB will automatically be used by Quartus II for a clock signal? So ALT_CLKCTRL is not necessary at all?
Third,
you should use the CCB to perform clock multiplexing.
By looking at Figure 5-1, if clock inputs are from FPGA clock pins or PLL outputs, then we can use CCB as a multiplexer. otherwise it's impossible, right?
Fourth
yes, you need to use create_generated_clock for the generated clocks.
Assume a clock is generated by internal logic, and in order to use global clock network, it has to pass through a CCB, right? (Do we need to use ALT_CLKCTRL in this case?) After the clock pass through a CCB, should it be treated as a generated clock and constrained? In other words, does the TimeQuest think a CCB changes clock timing?
Fifth,
I'm not sure TimeQuest will automatically handle the clock multiplexing done by the CCB. If it doesn't, check the 2nd clock multiplexing example:
By looking at the RTL schematic, the multiplexer is not implemented with a CCB.
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I'm a newbie in Altera FPGA. Sorry for these dumm questions and thank you for your helping.
Honored Contributor
