Questions about arrays declaring and initializing in VHDL

Hello. Now i should write on VHDL. And any things which was simple on Verilog is difficult on VHDL and i can't understand it.

I read many manuals but i don't know about right technics about work with arrays in VHDL.

I use Quartus II 13.0.

Underwritten simple example don't compile without errors and i 2 week can't solve this problem. If i can compile this project now, i will can compile all other projects in future.

Input is 2 bit number - "input_impulses". It checked on input clock - "clk", and this inputs changed array index - "array_index". And array index select element of array to output from this module. But i don't know what i was changed in code for good compilation. I rewrite many things but it is not work.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity code_on_vhdl is
    port (
        clk : in std_logic;
        input_impulses : in std_logic_vector (1 downto 0);
      output_impulses : out std_logic_vector (9 downto 0)
            );
end code_on_vhdl;
architecture Behavioral of code_on_vhdl is
signal array_index: std_logic_vector (1 to 0);
type array_type is array (3 to 0) of std_logic_vector (9 downto 0);
signal MY_ARRAY : array_type;
begin
MY_ARRAY <= (("0000000000"), ("1010101010"), ("1111001111"), ("1111111111"));
  
    process(clk)
    begin
        if rising_edge(clk) then
            if (input_impulses = "00") then
            array_index <= "00";
            else
                    if (input_impulses = "01") then
                    array_index <= "01";
                    else
                        if(input_impulses = "10") then
                        array_index <= "10";
                        else
                            if(input_impulses = "11") then
                            array_index <= "11";
                            end if;
                        end if;
                    end if;
            end if;
        end if;
    end process;
    output_impulses <= MY_ARRAY(to_integer (unsigned (array_index)));
end Behavioral;

I read about next rules and i change my code like this:

1) Array index is only integer value. They should be converted - "MY_ARRAY (to_integer (unsigned (array_index)))". For converting i connect "use ieee.numeric_std.all;".

2) I use aggregates for initialize array values - MY_ARRAY <= (("0000000000"), ("1010101010"), ("1111001111"), ("1111111111")); But i don't know how it writing, but this haven't errors in compilation.

3) And i need only this array - 4 piece of 10 bit std_logic_vector.

type array_type is array (3 to 0) of std_logic_vector (9 downto 0);

signal MY_ARRAY : array_type;

I can't use 4 piece of integer type. Because it have constrained by 32 bits, but my numbers in real projects have numbers more than 37 bit.

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Thanks in advance for any help.