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Altera_Forum's avatar
Altera_Forum
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11 years ago

Questions about arrays declaring and initializing in VHDL

Hello. Now i should write on VHDL. And any things which was simple on Verilog is difficult on VHDL and i can't understand it. I read many manuals but i don't know about right technics about wor...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

here is your problem:

signal array_index: std_logic_vector (1 to 0);

it is a null array, as 1 is higher than 0. I think you meant (1 downto 0)

Another point - why is array index a std_logic_vector? save your fingers from RSI, and make it:

signal array_index : integer range 0 to 3;