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I had something similar to the following code.
always @ (posedge a, posedge b)
begin
if(a)
begin
address <= address + 1;
end
else
begin
address <= 0;
end
end
'a' and 'b' are not clocks they are triggers. There is a separate clock that is used in separate state machines always blocks that run fine.
I was testing the code with signaltap and saw something that confused me.
Problem I was seeing is that address was incrementing on every clock cycle while ‘a’ was one ('b' was at zero) and not just when ‘a’ was transitioning from 0 to 1.
So with no posedges on either signal how could address be incrementing?
Thank you.....
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based on my rusty verilog I think you should put the adder below rather than at top as (a) is meant to be reset while clock is (b)
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