Question about True Dual Port RAM

can you please explain to me what does it mean to register an output or an input ? i searched the net but i can't find an example. I though that all the outputs when we do the assignment are called registered but i don't think this what it means isn't it ?

And before i could understand what did you mean i changed in the code below to get what i want :

library ieee;
use ieee.std_logic_1164.all;
entity merger is
	generic 
	(
		DATA_WIDTH : natural;
		ADDR_WIDTH : natural 
	);
	port 
	(
		clk		: in std_logic;
		addr_a	: in natural range 0 to 2**ADDR_WIDTH - 1;
		addr_b	: in natural range 0 to 2**ADDR_WIDTH - 1;
		data_a	: in std_logic_vector((DATA_WIDTH-1) downto 0);
		data_b	: in std_logic_vector((DATA_WIDTH-1) downto 0);
		we_a	: in std_logic :='1';
		we_b	: in std_logic:='1';
		q_a	: out std_logic_vector((DATA_WIDTH -1) downto 0);
		q_b		: out std_logic_vector((DATA_WIDTH -1) downto 0)
	);
end merger;
architecture rtl of merger is
	-- Build a 2-D array type for the RAM
	subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
	type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;
	-- Declare the RAM 
	shared variable ram : memory_t;
begin
	-- Port A
	process(clk)
	begin
	if(rising_edge(clk)) then 
		if(we_a = '1') then
			ram(addr_a) := data_a;
			q_a <= data_a;
		else
			q_a<=data_b;
		end if;
			
	end if;
	
	end process;
	-- Port B 
	process(clk)
	begin
	if(rising_edge(clk)) then 
		if(we_b = '1') then
			ram(addr_b) := data_b;
		end if;
  	   q_b <= ram(addr_b);
	end if;
	end process;
 
end rtl;

Is it okay i wrote it like this ? i disable the we_a whenever i want to update the content of the address and read directly the new data ( data_b) (using flags from other modules )