Questasim UVM macros

Hi ,

I am trying to compile and run simulation in Questasim , using uvm libraries and uvm packages.

But i am getting error that include files not defined , although these uvm files are installed in verilog_src folder at Questasim installed path.

See screen shots and sv files attached.

Any tip or guide how to direct compiler to pick the installed uvm files.

Thanks,

Regards,

# three files are :

package file :

////////////////////////
`include "uvm_macros.svh"
`include "uvm_pkg.sv"
package uvm_sim_pk;

import uvm_pkg::*;

class my_transaction extends uvm_sequence_item;

`uvm_object_utils(my_transaction)

rand int addr;
rand int data;
rand bit r0w1;

function new (string name = "");
// Without a string name the transaction would be anonymous
super.new(name);
endfunction: new

constraint c_addr { addr >= 0; addr < 256; }
constraint c_data { data >= 0; data < 256; }

endclass: my_transaction