Questasim UVM macros

yes in one module "dut" it was spelled wrong but still compilation results in error of not finding the uvm_pkg .

i have made some changes see below :

//uvm_sim_pk//

////////////////////////
`ifndef UVM_SIM_PK
`define UVM_SIM_PK

package uvm_sim_pk;
`include "C:/intelFPGA_lite/24.1std/questa_fse/verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh"
`include "C:/intelFPGA_lite/24.1std/questa_fse/verilog_src/uvm-1.1d/src/uvm_pkg.sv"
`include "uvm_macros.svh"
import uvm_pkg::*;

class my_transaction extends uvm_sequence_item;

`uvm_object_utils(my_transaction)

rand int addr;
rand int data;
rand bit r0w1;

function new (string name = "");
// Without a string name the transaction would be anonymous
super.new(name);
endfunction: new

///////////////////////////////////////////////////////////////////////////////////////////////

//top.sv//

`include "uvm_sim_pk.sv"
module top;

import uvm_sim_pk::*;

dut_if dut_if1 ();

dut dut1 ( .i_f(dut_if1) );

// Test classes are better placed in a package, but defining the class here
// avoids the need to introduce set_config_db to connect the virtual interface
// in this very simple example

//////////////////////////////////////////////////////////////////////////////////////////////

//dut.sv//

interface dut_if();
`include "uvm_pkg.sv"
`include "uvm_macros.svh"
import uvm_pkg::*;

int addr;
int data;
bit r0w1;

modport test (output addr, data, r0w1);
modport dut (input addr, data, r0w1);

////////////////////////////////////////////////////////////////////////

// do file //

## Questasim do file ##
vlib work
vlog -sv -work work +incdir+C:/intelFPGA/23.1std/questa_fe/verilog_src/uvm-1.1d/src uvm_tlm_imps.svh
vlog -sv -work work +incdir+C:/intelFPGA/23.1std/questa_fe/verilog_src/uvm-1.1d/src uvm_pkg.sv
vlog -sv -work work +incdir+C:/intelFPGA/23.1std/questa_fe/verilog_src/uvm-1.1d/src uvm_sim_pk.sv
vlog -sv -work work +incdir+C:/intelFPGA/23.1std/questa_fe/verilog_src/uvm-1.1d/src dut.sv
vlog -sv -work work +incdir+C:/intelFPGA/23.1std/questa_fe/verilog_src/uvm-1.1d/src top.sv

/////////////////////////////////////////////////////////////////////////

But i still this error :