Forum Discussion
Fpga_Egr_2025
Occasional Contributor
Occasional ContributorQuestasim UVM macros
Hi , I am trying to compile and run simulation in Questasim , using uvm libraries and uvm packages. But i am getting error that include files not defined , although these uvm files are installed in...
RichardT_altera
Super Contributor
Super ContributorAgain, you use the wrong command.
Use:
vlog -sv -work work +incdir+C:/intelFPGA_lite/24.1std/questa_fse/verilog_src/uvm-1.1d/src uvm_sim_pk.sv
Not
vlog -sv -work work +incdir+C:\intelFPGA_lite\24.1std\questa_fse\verilog_src\uvm-1.1d\src uvm_sim_pk.sv
That's likely what mess up the path name.
Regards,
Richard Tan
Fpga_Egr_2025Occasional Contributor
Occasional Contributori have also tried giving specific path in the .svh file like this :
////////////////////////
`include "C:/intelFPGA_lite/24.1std\questa_fse/verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh"
`include "C:/intelFPGA_lite/24.1std/questa_fse/verilog_src/uvm-1.1d/src/uvm_macros.svh"
`include "uvm_pkg.sv"
package sim_pk;
import questa_uvm_pkg::*;
import uvm_pkg::*;
But get this error :
