Questasim UVM macros

Here is the questasim compile result :

I then changed the do file script to include my modules i.e dut.sv and top.sv like this :

## Questasim do file ##
vlib work
vlog -sv -work work +incdir+C:/intelFPGA/23.1std/questa_fe/verilog_src/uvm-1.1d/src uvm_sim_pk.sv
vlog -sv -work work +incdir+C:/intelFPGA/23.1std/questa_fe/verilog_src/uvm-1.1d/src dut.sv
vlog -sv -work work +incdir+C:/intelFPGA/23.1std/questa_fe/verilog_src/uvm-1.1d/src top.sv

in my dut.sv : ------------------------------

import uvm_sim_pkg::*

interface dut_if();

int addr;
int data;
bit r0w1;

modport test (output addr, data, r0w1);
modport dut (input addr, data, r0w1);

endinterface: dut_if

module dut(dut_if.dut i_f);

always @(*)
begin
$display("DUT received r0w1 = %b, addr = %0d, data = %0d at %0t",
i_f.r0w1, i_f.addr, i_f.data, $time);
end

endmodule: dut

------------------------------------------------------------------------------------

in my top.sv : ------------------------------------------------------------------

`include "uvm_sim_pk.sv"
module top;

import uvm_sim_pk::*;

dut_if dut_if1 ();

dut dut1 ( .i_f(dut_if1) );

// Test classes are better placed in a package, but defining the class here
// avoids the need to introduce set_config_db to connect the virtual interface
// in this very simple example

class my_test extends uvm_test;

// my_test gets instantiated by means of the +UVM_TESTNAME command line argument and run_test()
`uvm_component_utils(my_test)

function new(string name, uvm_component parent);
super.new(name,parent);
`uvm_info("", "Called my_test::new", UVM_NONE);
endfunction: new

my_env m_env;

function void build_phase(uvm_phase phase);
super.build_phase(phase);
`uvm_info("", "Called my_test::build_phase", UVM_NONE);

// Always use the factory instead of new
m_env = my_env::type_id::create("m_env", this);
endfunction: build_phase

function void connect_phase(uvm_phase phase);
`uvm_info("", "Called my_test::connect_phase", UVM_NONE);

// Connect virtual interface in driver to actual interface
m_env.m_driver.m_dut_if = dut_if1;
endfunction: connect_phase

task run_phase(uvm_phase phase);
my_sequence seq;
`uvm_info("","Called my_test::run_phase", UVM_NONE);
seq = my_sequence::type_id::create("seq");
assert( seq.randomize() );
seq.start( m_env.m_sequencer );
endtask: run_phase

function void report_phase(uvm_phase phase);
`uvm_info("", "Called my_test::report_phase", UVM_NONE);
endfunction: report_phase

endclass: my_test

initial
// Calls static uvm_env::run_test to execute all test phases for all envs & top-level components
run_test("my_test"); // Requires +UVM_TESTNAME at run-time

endmodule: top

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questasim compile results :