Forum Discussion
Occasional ContributorQuestasim UVM macros
Super ContributorAgain, you use the wrong command.
Use:
vlog -sv -work work +incdir+C:/intelFPGA_lite/24.1std/questa_fse/verilog_src/uvm-1.1d/src uvm_sim_pk.sv
Not
vlog -sv -work work +incdir+C:\intelFPGA_lite\24.1std\questa_fse\verilog_src\uvm-1.1d\src uvm_sim_pk.sv
That's likely what mess up the path name.
Regards,
Richard Tan
Fpga_Egr_2025still its not working , i am getting error msg that questasim cannot open uvm_macros.svh in read mode.
Although i am running questasim in admin mode .
- RichardT_altera
I attached an example that I used.
Add these script into a .do file then run the .do file.vlib work
vlog -sv -work work +incdir+C:/intelFPGA/23.1std/questa_fe/verilog_src/uvm-1.1d/src my_transaction.sv- Fpga_Egr_2025
Here is the questasim compile result :
- Fpga_Egr_2025
i have also tried giving specific path in the .svh file like this :
////////////////////////
`include "C:/intelFPGA_lite/24.1std\questa_fse/verilog_src/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh"
`include "C:/intelFPGA_lite/24.1std/questa_fse/verilog_src/uvm-1.1d/src/uvm_macros.svh"`include "uvm_pkg.sv"
package sim_pk;
import questa_uvm_pkg::*;
import uvm_pkg::*;But get this error :
