Questasim INTEl EDITION counter simulation

Hello. I'm using this vhdl code to make an 8 bit counter with enable. Quetasim Intel fpga does not increment the counter regularly (defined as variable). It goes from 'X' to '1' and then it...

Simulation

roeekalinsky
2 years ago
@GOMEZ_IT, I think you were right, this looks like a simulator problem.
I was able to reproduce your original observation, and it appears to be a bug in older versions of Questa, up to the version shipped with Quartus Pro 23.3.
The version of Questa shipped with Quartus Pro 23.4 doesn't appear to exhibit this symptom. Or at least not with this test case. But I don't know if this was a known bug that got fixed, or if the symptom just went away with other changes in Questa. That's something you should confirm with Intel and/or Mentor/Siemens.
For ease of testing, I modified your test case slightly to be able to run in a more minimalist command line mode, with console messages in lieu of waveforms. See attached zip.
Running this test case with all the simulators I currently have available to me I got the following results:
Questa from Quartus Pro 22.2: bad
Questa from Quartus Pro 22.4: bad
Questa from Quartus Pro 23.1: bad
Questa from Quartus Pro 23.2: bad
Questa from Quartus Pro 23.3: bad
Questa from Quartus Pro 23.4: good
Modelsim DE 2022.4: good
ghdl 4.0.0-dev: good
See attached log.txt for the above results.
-Roee
questa_bug.zip2 KB
log.txt18 KB

roeekalinsky

Contributor

2 years ago

Looks like I was mistaken. An initial value at the variable declaration in the process takes effect at time zero, not at every entry into the process. Learn something every day.

But now, the mystery deepens. This explains why it does work, but it doesn't explain why your original example didn't work. And in fact, simulating it both ways on my end, I see it work in both cases. I can't reproduce your original result of it not working.

You didn't share your test bench, so I created a simple one to simulate it on my end. I'm curious if the crux lies in how you're generating the inputs to this module, if there is some gotcha there somehow. Can you please share your test bench code?