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KVino1
New Contributor
New ContributorQuesta/Modelsim, long SV variable in object
Hi, I have the same problem on Intel free Modelsim and both in Commercial Questasim CADs. Here's my SystemVerilog signals, I want to check in simulator logic [8191-1:0] ram_buffer0 ;
logic...
Vicky1
Regular Contributor
Regular ContributorHi,
Can you share the project file or row_buffering_tb.sv file, if possible?
Best Regards
Vikas Jathar
(This message was posted on behalf of Intel Corporation)
