Forum Discussion
Questa Starter Edition 25.1 - svverification license checkout fails (valid license per lmdiag)
Hi, I'm running Questa*-Altera FPGA Starter Edition 25.1std on Windows 10.
My design compiles and elaborates successfully, but simulation fails when
loading a testbench that uses SystemVerilog classes, randomize(), and
covergroup:
** Error: Failure to checkout svverification license feature.
** Error: (vsim-1) Unable to checkout verification license - required for
testbench features (randomize, randcase, randsequence, covergroup).
License details:
- License: SW-QUESTA (Non-Commercial Software SW-QUESTA), FIXED, NIC ID
- Feature: intelqsimstarter, v2027.01
- Node-locked correctly to my machine's NIC ID (confirmed via lmutil lmdiag)
- License Expires: 26-Jul-2027, currently active and valid
lmutil lmdiag output confirms the license is valid and correctly bound:
"intelqsimstarter" v2027.01, vendor: mgcld, expiry: 26-jul-2027
uncounted nodelocked license, locked to ethernet address "d053493e9348"
starts: 26-jul-2026, expires: 26-jul-2027
This is the correct node for this node-locked license
Both LM_LICENSE_FILE and SALT_LICENSE_SERVER are correctly set to the
license file path (verified spelling, no typos, no spaces in path, full
system restart performed). The GUI itself launches without any license
error - the failure only occurs specifically when loading a design that
uses randomize/covergroup.
Is svverification/testbench verification simply not included under the
free Starter Edition license (intelqsimstarter), or is there an additional
configuration step needed to enable it? Any guidance appreciated.
1 Reply
- RichardT_altera
Super Contributor
Yes, you are right that the Questa Altera FPGA Edition does not support advanced verification features. Please refer to the Knowledge Base article below for details:
Error: (vsim-1) Unable to checkout verification license - required for testbench features (randomize, randcase, randsequence, covergroup) | Altera Community - 341859Error: Failure to checkout svverification license feature. | Altera Community - 342760
Any SV verification constructs (randomize, randcase, randsequence, covergroup) require you to use Siemens EDA QuestaSim*. (non-FPGA edition)
Regards,
Richard Tan