I run a Questa simulation for an IP core from the command line on a Linux server. Usually, the simulation finishs successfully. But every now and then the simulation hangs.When it hangs, I can see that the CPU load is 100% but I can't break the simulation by hitting Ctrl-C. The key-press is detected ("# Break key hit") but the simulation won't halt.Since I use the same seed for random number generation in each run, this seems like nondeterministic behavior.I have no clue, where this behavior is comming from. Are there any command line options that I can use to get closer to the problem? How can I go one with debugging in such a case?

I tried to run all processes with valgrind. This causes the simulation to terminate with:"Process terminating with default action of signal 41 (SIGRT9)"and"Trouble with Simulation Kernel."Of course, this might be a side effect of valgrind.

I tried a testbench from another project with valgrind and it works fine. So it seems there is really something wrong with the simulator.

I was able to reproduce the hang up on a Windows system.In contrast to the Linux system I was able to stop the process with Ctrl-C leading to the following output:vish lost connection to vsim process. simulator: Unexpected EOF on RPC channel sock0000000007A71780 Kernel lost connection to front end process. ** Fatal: Exiting VSIM license process.

As it worked fine after you changed the project, the error may related to the project and testbench. It may be that your project got stuck during simulation, causing excessive CPU resource usage.You may check your testbench to see if there are any operations that cause an infinite loop.

Thanks for the reply.Questa is able to detect zero delay loops, so I should see an error about this. Furthermore, most of the time the tests run just fine. I have to run a single test a few hundred times to cause this behavior. That means it is nondeterministic behavior. If there is an infinite zero delay loop I should see the hang up in every simulation run.Besides that, I should be able to break/pause simulation in such a loop, which does not work either.

Questa simulation hangs (nondeterministic)

37 Replies

TingJiangT_Intel
Contributor
2 years ago
Sorry for the delayed response, can you help share the script and specify the lines causing the error. Thanks.
TingJiangT_Intel
Contributor
2 years ago
Hi there, is there any updates
- c-thaler
  Occasional Contributor
  2 years ago
  Hi,
  sorry for the late reply, I've been on vacation for 2 weeks.
  I attached the generated script to this post. The error is caused by line 14:
  # ** Error: (vcom-11) Could not find work.th_dnx_simpledualportram.
  "th_dnx_simpledualportram_bhv_a.vhd" contains the architecture definition of th_dnx_simpledualportram.
  However, the entity definition is in "th_dnx_simpledualportram_e.vhd", which is compiled in line 17.
  I think, this is the wrong compile order.
  questa_hang_up_run_msim_rtl_vhdl.7z2 KB
TingJiangT_Intel
Contributor
2 years ago
Hi there, thanks for the information. Could you please help specify what steps you do when generating the script.
BTW, you may try to change the files order in the 'setting - files'. Try to move this file to the top of the list to see if it helps.
- c-thaler
  Occasional Contributor
  2 years ago
  First, I do "Analysis & Synthesis" for the project. Then I go to "Tools -> Run Simulation Tool -> RTL Simulation". Then Questa comes up and fails while compiling the sources.
  The file order in "Settings -> Files" is correct. The file order in the script is different than what I see in "Settings -> Files".
TingJiangT_Intel
Contributor
2 years ago
I see. Could you help provide the project for reproducing the issue? Let me check whether it's a software issue.
- c-thaler
  Occasional Contributor
  2 years ago
  I've sent you a mail with a link to our file exchange server. Please download the project from there.
TingJiangT_Intel
Contributor
2 years ago
Hi there, I have tried to reproduce the issue with the file you provided but failed in the first step and shows the follow message:
Error (12007): Top-level design entity "shipment" is undefined
Seems that some files are missing.
- c-thaler
  Occasional Contributor
  2 years ago
  I fixed an issue with the revision name that caused the 12007 error. It should work now. I've sent you a mail with a link to our file exchange server. Please download the project from there.
lishilton
New Contributor
2 years ago
ohh, I get it
TingJiangT_Intel
Contributor
2 years ago
Hi thaler, Sorry for the delayed response as I just back from leaving. The shared link has expired. Could you please share it again.
TingJiangT_Intel
Contributor
2 years ago
Hi Thaler, I tried to modify the file as what you showed, but it caused error during simulation as follow:
** Error: (vcom-11) Could not find work.th_dnx_genericram.
Can you share the '.do' file works in your side, thanks
- c-thaler
  Occasional Contributor
  2 years ago
  I was able to fix the do file. Now the simulation can be run. Please find attached the do file.
  
  Unfortunately Quartus generates absolute paths in it. But if you compare your and my do-file you should be able to do the same changes to yours.
  questa_comp_order_run_msim_rtl_vhdl.7z2 KB
TingJiangT_Intel
Contributor
2 years ago
I tried your updated example, and it works well. Thanks a lot for your sharing.
- c-thaler
  Occasional Contributor
  2 years ago
  Hi TingJiangT,
  Any progress on this? Were you able to reproduce the hangups?
c-thaler
Occasional Contributor
11 months ago
It seems like this case has been closed by support. However, I'm still looking for a solution for this issue.

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Questa simulation hangs (nondeterministic)

37 Replies

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