Questa intel FPGA has no delay to Gate level simulation

I'm missing the step where you import the gate level netlist.

It doesn't look like you are running a gate-level sim. It looks like a standard RTL sim.

That seem to be rtl simulation. And also, it is always better to use sta for timing instead gate level for timing.

Let me know if there is any update

Maybe you need to synthesize the RTL first?

Finally, I found that I should turn off "Generate functional simulation netlist", then the gate level simulation will display correctly.

ref: https://www.youtube.com/watch?v=HFWd7QPibMY&t=400sh

Thank to everyone.

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