hokagechichi
New Contributor
New ContributorQuesta intel FPGA has no delay to Gate level simulation
I used Cyclone IV (EP4CE6E22C8), and the delay should be 9ns. However, my Gate level simulation's delay was 0. What should I do?
Forum Discussion
SyafieqS
Super Contributor
Super ContributorThat seem to be rtl simulation. And also, it is always better to use sta for timing instead gate level for timing.
