RayHaynes1
Occasional Contributor
Occasional ContributorQuesta and preprocessor defines
I'm trying to use some common verilog source files for both an Altera build and another FPGA manufacturer's build. A different path to the parameters.v file is required for each of the builds. I have...
Ok figured out a way. Add this to the end of the vlog command for each file that requires that define. Would have been nice to figured out how to set this via a source file but this works.
vlog ./../verilog/sourcefile.v +define+pAlteraBuild=1
