Questa and preprocessor defines

I'm trying to use some common verilog source files for both an Altera build and another FPGA manufacturer's build. A different path to the parameters.v file is required for each of the builds. I have the code below at the top of each of my common source files. But even though the fpgaBuildParameters.v file defines pAlteraBuild the preprocessor does not see that define and so it incorrectly takes the `else path. I'm sure this is because of how the preprocessor works but I can't figure out a way to do this.

I don't want keep 2 copies of the common files just because of the path and I can't easily make the path the same for both builds. There has to be some trick to do this.

`include "fpagBuildParameters.v" // Defines pAlteraBuild
`ifdef pAlteraBuild // This is set in the fpagBuildParameters.v
    `include "./../common_verilog/Parameters.v"
`else // Other manufacturer build
    `include "./../../common_verilog/Parameters.v"
`endif

Thanks in advance,

Ray Haynes