Query related to I2C slave IP and SDM IP

Hi Jingyang,

Purpose of I2C Slave in our project is as below:

BMC Controller on Board will read the temperature, health status of FPGA via the I2C bus. BMC Controller requests the status via I2C Bus connected to I2C slave. I2C Slave then sends this request to Processor. Processor in turn gathers the relevant information and provides the status back to I2C Slave which in turn passes this information to BMC controller via I2C bus.

The I2C Slave with memory mapped master agent will not solve the purpose.

There is I2C Slave IP comes along with the processor which acts as a processor subsystem IP and it is present in SDM component. If we use the in-built SDM infrastructure of Intel FPGA, we will get our purpose solved. But in our project, we are using our own Processor and not the SDM structure. Thus we need I2C Slave IP component which is exactly same as the one gets enabled when we use in-built SDM architecture.

Thus I think, below infrastructure that you had suggested won't help here:

Avalon Agent >>> AXI Bridge Master --- AXI Bridge Slave >>> AXI Master Port

Also can you comment on mailbox-client IP integrated as a bridge between processor and SDM [SDM: Secure Device Manager is used to access Flash] ?

In case of more understanding, we can have a call.

Regards

Sneha

Hi Jingyang,

Any updates ?

I have one more query. I.e. How to address map the HPS I2C IP in the address range of FPGA Fabric master ?

For example, consider I have JTAG to Avalon Master or any third party processor [Not the ARM processor in HPS system]. Now I need to program registers inside HPS I2C IP master using the above mentioned master. So I would need to know address space of the HPS I2C IP.

Kindly reply as soon as possible, as I am stuck in the middle of project.

Regards

Sneha

Hi Jingyang,

Timing is suitable and I have joined the meeting.

Regards

Sneha

Hi Jingyang,

We won't be able to use the I2C (Host) Core IP as it is the I2C master IP. We are looking for I2C Slave IP. Thus I think, only option remaining is the I2C IP in HPS subsystem that is programmed to behave as slave. I am able to find out HPS IPs registers with the help of following link:

https://www.intel.com/content/www/us/en/programmable/hps/agilex/hps.html

But I was not able to find out programming sequence of I2C Hard IP component.

For our second doubt, i.e. how to address map the bigger region with smaller address width, I am able to find out the address span expander logic.

I have integrated the system and would like to show you the system and would like to take your opinion.

Can we have a call on Monday IST 10 am or any suitable time that overlaps with your and mine time zone ?

Regards

Sneha

Yes, that is the reason, we can not have this I2C with Avalon Memory mapped host IP in our project subsystem.

Thus we thought of using the I2C HPS IP which can be programmed both as master or slave.

I did get the register document of this IP but did not get the programming sequence of the IP. Can you let me know from where I can get this ?

Also I2C HPS IP can work in multi-master mode if programmed as master ?

Regards

Sneha

Thanks Jingyang.

Now I think, I2C related queries are resolved. I also got the document for HPS peripherals at the intel site. Able to integrate the HPS subsystem.

I will need some help to clear my understanding related to mailbox client. Keeping this post open till that time.

Regards

Sneha