Forum Discussion
Hi Snehar
Great talking to you in the call and better understand what is your problem.
The IP you are looking for should be the " Intel FPGA Avalon® I2C (Host) core"
You could find the details below the link here:
https://www.intel.com/content/www/us/en/docs/programmable/683130/22-1/fpga-i2c-host-core.html
Regards
Jingyang, Teh
Hi Jingyang,
We won't be able to use the I2C (Host) Core IP as it is the I2C master IP. We are looking for I2C Slave IP. Thus I think, only option remaining is the I2C IP in HPS subsystem that is programmed to behave as slave. I am able to find out HPS IPs registers with the help of following link:
https://www.intel.com/content/www/us/en/programmable/hps/agilex/hps.html
But I was not able to find out programming sequence of I2C Hard IP component.
For our second doubt, i.e. how to address map the bigger region with smaller address width, I am able to find out the address span expander logic.
I have integrated the system and would like to show you the system and would like to take your opinion.
Can we have a call on Monday IST 10 am or any suitable time that overlaps with your and mine time zone ?
Regards
Sneha