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Altera_Forum's avatar
Altera_Forum
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9 years ago

Quatus TCL Integration with Assignments

So I'm trying to build a date/time register that is updated every build. I was going to use a TCL script to generate a global assignment, and then use that global_assignment in my VHDL code as a register value.

The question is: is this even possible? I understand how to get scripts to run (https://www.altera.com/support/support-resources/design-examples/design-software/tcl/auto_processing.html), but how can I pull assignments in to my HDL?

EDIT: Sorry about the bad thread title. Hopefully an admin can come around and fix it.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    No, you cannot access global_assignments from VHDL.

    However, you can have TCL spit out some VHDL (a package for example) with some constants in it that set the values of some registers.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    --- Quote Start ---

    No, you cannot access global_assignments from VHDL.

    However, you can have TCL spit out some VHDL (a package for example) with some constants in it that set the values of some registers.

    --- Quote End ---

    That's a great idea. I'll instantiate a block is generated by a TCL script to spit out a constant. That's an acceptable workaround. I'm surprised there isn't a megafunction for "build time".
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    --- Quote Start ---

    That's a great idea. I'll instantiate a block is generated by a TCL script to spit out a constant. That's an acceptable workaround. I'm surprised there isn't a megafunction for "build time".

    --- Quote End ---

    Works great. Automatic VHDL generation. Easy enough to add Verilog. If anyone is interested in the files, just let me know.