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Altera_Forum's avatar
Altera_Forum
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9 years ago

Quatus TCL Integration with Assignments

So I'm trying to build a date/time register that is updated every build. I was going to use a TCL script to generate a global assignment, and then use that global_assignment in my VHDL code as a regi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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That's a great idea. I'll instantiate a block is generated by a TCL script to spit out a constant. That's an acceptable workaround. I'm surprised there isn't a megafunction for "build time".

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Works great. Automatic VHDL generation. Easy enough to add Verilog. If anyone is interested in the files, just let me know.