New Contributor
New ContributorI guess I am not following properly. See attached screenshot. This is from Intel's reference design for the Verification IP Suite. The top IP that contains the clk/rst is what's missing from the current IP list. I thought this was the Clock Source BFM and Reset Source BFM but updated and split into two separate IP.
Thinking about it now, I'm assuming I can just replace this with a Clock Bridge and Reset Bridge to replicate it? And my other question would be what is the purpose of the clock and reset BFMs then when it is not being driven by the test bench? This is very new to me so I am trying to piece this together and understand it.
