BTayl147
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New ContributorQuartus Timing Analyzer and Constraints...
I realize this is a lot to ask however, I'm not understanding completely how to constrain this project. Attached is a simplified version of my project. It uses an address bus, data bus, read and wr...
Hi,
I tried to search internally, I could not find an example of constraining a SRAM. Could you check the document in https://forums.intel.com/s/question/0D50P00003yyGvhSAE/timequest-constrains-for-async-sram.
Hope it helps. Please let me know if this is not what you are looking for.
Thanks.
Best regards,
KhaiY
