New Contributor
Super ContributorI’ve received the design, but it appears to be in Quartus Pro 25.1. Could you confirm if that’s correct?
I’m asking because we were discussing NativeLink simulation in the previous replies, which is a feature not supported in Quartus Pro.
Regards,
Richard Tan
New ContributorHello Richard,
Thank you for your insight. I reflected on my HDL simulation workflow, and I realized that I haven't been using correct terminology in our conversation.
- I'm using Quartus Prime Pro v25.1, which when I checked, doesn't support NativeLink simulation flow.
- The simulation flow I've been using is the following. While it is not NativeLink, I believe it follows the suggested simulation flow with Quartus Prime Pro:
1. Register all design files (including IPs) in the Quartus Prime Pro project by selecting [ Project menu > Add/Remove Files in Project ]
2. Set the path for EDA tool executable program in [ Tools > Options > EDA tool options ]
3. Set board and IP settings in [ Assignments > Settings > Board and IP settings ]
4. Set simulation settings in [ Assignments > Settings > EDA Tool Settings > Simulation ]
5. Register test bench in [ Assignments > Settings > EDA tool settings > Simulation > Testbench ]
6. Generate simulation scripts for IP by selecting [ Tools > Generate simulator setup script for IP ]
Following through these steps (sometimes in different order) and running [ Tools > Run Simulation > RTL Simulation ] created a .do file which I ran with Intel Questa FPGA Edition, where I experienced compilation errors relating to missing package files (which were listed in the .do file).
What confused me about troubleshooting is the following:
- I tried this Intel tutorial, which worked even on Quartus Prime Pro, so I'm assuming that [ Tools > Run Simulation > RTL Simulation ] might not have been the issue (https://www.intel.com/content/www/us/en/docs/programmable/703090/21-1/simulation-quick-start.html)
- Some package files are not being found when compiling in Intel Questa FPGA Edition, even though they are present at the directories mentioned in the .do file
For my project (which involves several IPs), should I have used the scripted flow instead, as recommended in the links below? (I've found several Macnica support links handy, though they had to be translated into English from Japanese)
https://www.macnica.co.jp/en/business/semiconductor/articles/intel/133550/
https://www.macnica.co.jp/en/business/semiconductor/articles/intel/146968/
https://www.intel.com/content/www/us/en/docs/programmable/730191/25-1/commands-to-compile-elaborate-and-simulate.html
I apologize for some confusion in the use of terminology.
