Quartus-Questa Compilation Simulation Dependency Management

I believe you are using Quartus Standard Edition and attempting to simulate using the Nativelink simulation flow.

Typically, when we run Tools → Run Simulation → RTL Simulation, the Quartus Standard Edition software automatically launches the Questa Altera Edition simulator and simulates the testbench file according to the specifications set in the Simulation settings.

I have not encountered any dependency ordering issues when using Nativelink.

Does the issue occur when you try to execute the .do file manually during simulation?

For example:

do PLL_RAM_run_msim_rtl_verilog.do

You may want to try running the example design (quartus-std-lite-pll-ram) provided in the user guide, following the steps and guidance described in the document.

Lite/Standard Edition:

https://www.intel.com/content/www/us/en/docs/programmable/703090/21-1/simulation-quick-start.html

Regards,

Richard Tan