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xxerexxaa's avatar
xxerexxaa
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2 years ago

Quartus Prime20.1 can't compile systemverilog syntax

我在使用modsim编译成功并且成功仿真以后想使用quartus烧录至FPGA上发现许多类似于class 和数学函数的使用在quartus里无法编译。 我已经修改了quartus prime 20.1 的编译器为SystemVerilog但是还是无法编译class。请问有人遇到类似的情况吗？ 据我所知可能是软件本身的问题，但是我的导师希望我最好还是使用quartus，所以请问有什么比较好的不...
Hdl
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,

System Verilog synthesis support is specified in Quartus help. Section 8 Classes isn't supported at all.

Your math functions are possibly not synthesizable, e.g. ieee.math_real functions.

  • xxerexxaa's avatar
    xxerexxaa
    Icon for New Contributor rankNew Contributor
    2 years ago

    请问有没有办法能让quartus获得支持或者使用能适配SystemVerilog的软件呢？

    Is there any way to get support from quartus or to use other softwares that can be adapted to SystemVerilog?

    • FvM's avatar
      FvM
      Icon for Super Contributor rankSuper Contributor
      2 years ago
      Hi,
      I don't think it's a matter of the tool. Dynamic data and code definition can't be mapped to logic hardware. Nested (recursive) definitions can be used in generate constructs, but they are translated to parallel logic at compile time. If the recursion count isn't limited somehow, the construct isn't synthesizable.