New Contributor
Super ContributorIt doesn't seem like it, but you don't have any spaces anywhere higher in your file hierarchy? Probably not since this is the only file it complains about, but you can't have any spaces in the path nonetheless.
I'm curious though why the warning/error is thinking this is a VHDL file. Do you have a reference to it in a library or setting as a VHDL file?
New ContributorI definitely do not have any spaces anywhere in my file hierarchy.
Furthermore, I do not know why Questa is considering the MIF file to be a 'VHDL', as I am not intentionally specifying the MIF anywhere in my project as a VHDL file. Again, note that simply by regenerating the RAM module using the MIF located under the root folder the problem goes away (and no other changes).
Another piece of information is that the simulation problem does not occur during compilation of the source code, but once the simulator starts running and then trying to read/access the MIF file for the initialization values.
