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WGao1's avatar
WGao1
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4 months ago

Quartus Prime Pro 25.1.0 Reports Unconstrained Paths in Cyclone 10GX PCIe Hard IP

Hi, Recently I have installed Quartus Prime Pro 25.1.0 and recompiled a Cyclone 10GX design that was originally compiled in Quartus Prime Pro 20.1.0. All IP's were updated automatically in 25.1.0. T...
Timing
WGao1's avatar
WGao1
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4 months ago

After digging a bit more, I have found that the xcvr fpll within the PCIe IP is missing after synthesis. Therefore no clocks are generated for the PCIe IP.

This is caused by Quartus failing to identify the architecture in the generated file "PCIE_IP_altera_pcie_a10_hip_altera_xcvr_fpll_a10_2020_tg4rxbi.vhd". The warning messages are -

There are no errors in this file. It is identical to the equivalent file generated in version 20.1.0.

This looks like a bug in version 25.1.0. It might be related to the long entity name.