Siyeon
New Contributor
New ContributorQuartus prime lite edition 20.1.1 gate level simulation
I want to perform gate level simulation in Quartus Prime Lite Edition.
After selecting "Tools → Run simulation tool → gate level simulation" and viewing the ModelSim waveforms, I noticed that the data arrives exactly on the clock edges.
It seems like the electron movement time is not being considered. I'm wondering if I made a wrong option selection or if timing information is not supported in this version.
I tried running a simulation with the following simple Verilog code.
module seq_model(b,rstb,clk,a);
output reg b;
input rstb, a, clk;
always @(posedge clk or negedge rstb)
if(!rstb)
b <= 0;
else
b <= a;
endmodule
I generated and provided all input signals directly in ModelSim for the simulation. The "clk" signal repeats every 10 ns, the "rstb" signal is 0 from 0 to 15 ns and 1 afterward, and the "a" signal follows a clock-like pattern repeating every 20 ns.
