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Altera_Forum
Honored Contributor
7 years ago --- Quote Start --- In build.bat file you need to add -gvhdl as a compiler option to i++. So it should be look like i++ -march="fpgafamily" -gvhdl counter.cpp -o test-fpga.exe Then build test-fpga and run test-fpga.exe. This will create a simulation file under verification folder. Finally, open the verification\vsim.wlf file with Modelsim. --- Quote End --- I have encountered an error when I did this. I have opened a new thread for this problem here: https://www.alteraforum.com/forum/showthread.php?t=58394&p=237529#post237529 Please post your comments there.